1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to a LCD device and a method of driving the same, wherein generation of a horizontal stripe phenomenon may be prevented.
2. Description of the Related Art
Generally, liquid crystal display (LCD) devices control light transmittance characteristics of liquid crystal material in accordance with applied electric fields. Accordingly, LCD devices typically include an LCD panel having a plurality of liquid crystal cells arranged in a matrix pattern, and drive circuits to drive the plurality of liquid crystal cells.
FIG. 1 illustrates a related art liquid crystal display (LCD) device.
Referring to FIG. 1, the related art includes an LCD panel 12 having a plurality of liquid crystal cells 20 arranged in a matrix pattern, a gate diver 14 for driving a plurality of gate lines GL1 to GLn, a data driver 16 for driving a plurality of data lines DL1 to DLm, and a timing controller 18 for controlling the gate and data drivers 14 and 16, respectively. The LCD panel 12 further includes a plurality of thin film transistors (TFTs) formed at crossings of the plurality of gate and data lines GL1 to GLn and DL1 to DLm, respectively, wherein each of the TFTs is connected to a corresponding liquid crystal cell 20.
Upon driving the plurality of liquid crystal cells 20, the gate driver 14 sequentially applies scan signals to the plurality of gate lines GL1 to GLn to sequentially drive rows of liquid crystal cells 20. Accordingly, the scan signals include gate high and low voltages (VGH) and (VGL), respectively. Whenever the gate high voltage (VGH) is applied to a gate line (GL), TFTs within the driven row of liquid crystal cells are turned on and pixel signals, applied by the data driver 16 to each of the data lines DL1 to DLm, are transmitted to the driven row of liquid crystal cells 20. Whenever the gate low voltage (VGL) is applied to a gate line (GL), TFTs within the driven row of liquid crystal cells 20 are turned off, wherein a voltage corresponding to a pixel signal remains charged within the liquid crystal cell 20.
Each liquid crystal cell 20 can be equivalently represented as a liquid crystal capacitor (Clc) including a common electrode capacitively coupled to a pixel electrode by liquid crystal material having anisotropic dielectric properties, wherein the pixel electrode is connected to a TFT. Each liquid crystal cell 20 further includes a storage capacitor (Cst) formed between a pixel electrode and a pre-stage gate line for retaining a voltage associated with a pixel signal until a subsequent pixel signal is charged to the liquid crystal cell 20. Once a pixel signal is applied from a data line (DL), a turned-on TFT applies a voltage associated with the pixel signal to the pixel electrode to generate electric field between the pixel and common electrodes. In response to the generated electric field, a molecular orientation of the liquid crystal material is manipulated such that light transmittance characteristics of the liquid crystal cell are controlled. Moreover, gray scale values of light are realized by the liquid crystal cell by adjusting the pixel signal voltage.
The gate driver 14 sequentially applies the gate high voltage (VGH) to the plurality of gate lines GL1 to GLn in response to gate control signals (GSP, GSC, GOE) outputted from the timing controller 18. More specifically, the gate driver 14 generates a shift pulse by shifting a gate start pulse (GSP) in accordance with a gate shift pulse (GSC). Next, the gate driver 14 applies the gate high voltage (VGH) to a predetermined gate line (GL) during each horizontal period in response to the gate shift pulse (GSC). During operation, the gate driver 14 applies the gate high voltage (VGH) only during an enable period of a gate output enable signal (GOE). During periods of time when the gate high voltage (VGH) is not applied, however, the gate driver 14 applies the gate low voltage (VGL) to the gate lines GL1 to GLn.
The data driver 16 applies pixel signals, specific for each gate line to which the gate high voltage (VGH) is applied, simultaneously to each of the data lines DL1 to DLm in response to data control signals (SSP, SSC, SOE, POL) outputted from the timing controller 18. More specifically, the data driver 16 generates a sampling signal by shifting a source start pulse (SSP) in accordance with a source shift clock (SSC). Next, the data driver 16 sequentially receives and latches digital pixel data (R,G,B) outputted from the timing controller 18 in response to the sampling signal. The data driver 16 then converts the digital pixel data (R,G,B), latched in correspondence with the gate line to which the gate high voltage (VGH) is applied, into analog pixel signals and applies the analog pixel signals to the data lines DL1 to DLm during the enable period of the source output enable signal (SOE). More specifically, the data driver 16 converts the digital pixel data (R,G,B) into analog pixel signals using gamma signals outputted from a gamma voltage generator (not shown). The data driver 16 also converts the digital pixel data (R,G,B) into positive and negative polarity pixel signals in response to a polarity control signal (POL). For example, in response to the polarity control signal (POL), the data driver 16 inverts the polarity of the pixel signal based on a columnar arrangement of the liquid crystal cells 20 to drive the liquid crystal display panel 12 according to a dot inversion system.
As mentioned above, the timing controller 18 controls the gate and data drivers 14 and 16 by generating the gate control signals (GSP, GSC, GOE) and the data control signals (SSP, SSC, SOE, POL), respectively. Additionally, the timing controller 18 arranges the pixel data (R,G,B) and applies the arranged digital pixel data to the data driver 16.
As described above, liquid crystal cells 20 within the related art LCD display can be driven using an inversion driving method such as a frame inversion, line (column) inversion, or dot inversion method to improve a picture quality of the LCD device. Compared to other inversion driving methods, the dot inversion driving method provides an excellent picture quality. However, and as shown with reference to FIG. 2, use of the dot inversion driving method can generate defects, such as horizontal stripes, within the LCD panel 12. As described in greater detail below, the horizontal stripe phenomenon occurs due to the presence of first and second parasitic capacitors Cdp1 and Cdp2 formed between pixel electrodes 20 of liquid crystal cells A and B and preceding and succeeding ones of adjacent data lines (e.g., data lines DLk and DLk+1).
The horizontal stripe phenomenon, generated when the liquid crystal display panel is driven according to the dot inversion driving method, will now be explained in greater detail with reference to FIGS. 3 to 5.
FIG. 3 illustrates charging characteristics of vertically adjacent liquid crystal cells with respect to pixel signals applied to the kth data line shown in FIG. 2. FIG. 4 illustrates charging characteristics of vertically adjacent liquid crystal cells with respect to pixel signals applied to the (k+1)th data line shown in FIG. 2. FIG. 5 illustrates charging characteristics of vertically adjacent liquid crystal cells with respect to pixel signals applied to the kth and (k+1)th data lines shown in FIG. 2.
Referring to FIGS. 2 to 5, during a first horizontal period, a first pixel signal (−Vp), having a negative polarity (−) with respect to the common voltage Vcom, is applied to the kth data line (DLk) while a first pixel signal (+Vp), having a positive polarity (+) with respect to the common voltage Vcom is applied to the (k+1)th data line (DLk+1). The brightness level represented by the first positive polarity pixel signal (+Vp) is relatively higher than the brightness level represented by the first negative polarity pixel signal (−Vp). Simultaneously with the application of the first negative and positive polarity pixel signals −Vp and +Vp, a first thin film transistor (TFT1), connected to the first gate line (GL1), is turned on in response to a scan pulse (not shown) applied to the first gate line (GL1). Accordingly, a first negative pixel voltage Vp1, associated with the first negative polarity pixel signal (−Vp), is charged to the first liquid crystal cell (A) connected to the first gate line (GL1) from the kth data line (DLk).
Subsequently, during a second horizontal period (H2), a second pixel signal (+Vp), having a positive polarity (+) with respect to the common voltage Vcom, is applied to the kth data line (DLk) while a second pixel signal (−Vp), having a negative polarity (−) with respect to the common voltage Vcom is applied to the (k+1)th data line (DLk+1). The brightness level represented by the second negative polarity pixel signal (−Vp) is relatively higher than the brightness level represented by the second positive polarity pixel signal (+Vp). Simultaneously with the application of the second positive and negative polarity pixel signals +Vp and −Vp, a second thin film transistor (TFT2), connected to the second gate line (GL2), is turned in response to a scan pulse (not shown) applied to the second gate line (GL2). Accordingly, a second positive pixel voltage Vp2, associated with the second positive polarity pixel signal (+Vp), is charged to the second liquid crystal cell (B), connected to the second gate line (GL2), from the kth data line (DLk).
As a result of driving the related art LCD panel as described above, the first negative pixel voltage Vp1 is capacitively affected by the second positive polarity pixel signal (+Vp) applied to the kth data line (DLk) via the first parasitic capacitor (Cdp1) and by the second negative polarity pixel signal −Vp applied to the (k+1)th data line (DLk+1) via the second parasitic capacitor (Cdp2) during the second horizontal period (H2). Accordingly, a value of the first negative pixel voltage Vp1 changes during the second horizontal period (H2). Since an absolute value of the second negative polarity pixel signal −Vp applied to the (k+1)th data line (DLk+1) is relatively large, the capacitance of the second parasitic capacitor (Cdp2) is also relatively large, thereby increasing the magnitude of the first negative pixel voltage Vp1 within the first liquid crystal cell (A).
Moreover, during a third horizontal period (H3), a third negative polarity pixel signal (−Vp) is applied to the kth data line (DLk) to charge a third liquid crystal cell (not shown) while a third positive polarity pixel signal (+Vp) is applied to the (k+1)th data line (DLk+1). The brightness level represented by the third positive polarity pixel signal (+Vp) is relatively higher than the brightness level represented by the third negative polarity pixel signal (−Vp). Accordingly, the first negative pixel voltage Vp1 and the second positive pixel voltage Vp2 are both capacitively affected by the third negative and positive polarity pixel signals −Vp and +Vp respectively applied to the kth and (k+1)th data lines (DLk) and (DLk+1), respectively, via the first and second parasitic capacitors Cdp1 and Cdp2, respectively, during the third horizontal period (H3). Accordingly, a value of the first negative and second positive pixel voltages Vp1 and Vp2 change during the third horizontal period (H3). Since an absolute value of the third positive polarity pixel signal +Vp applied to the (k+1)th data line (DLk+1) is relatively large, the capacitance of the second parasitic capacitor (Cdp2) is also relatively large, thereby positively decreasing the magnitude of the first negative pixel voltage Vp1 and positively increasing the magnitude of the second positive pixel voltage Vp2.
As can be seen from the discussion above, the various positive and negative polarity pixel signals, charged within each liquid crystal cell, capacitively affect existing positive and negative pixel voltages, previously charged via the kth and (k+1)th data lines (DLk) and (DLk+1) through the first and second parasitic capacitors Cdp1 and Cdp2 within each liquid crystal cell. Moreover, due to the presence of the aforementioned polarity control signals (POL) applied to the kth and (k+1)th data lines (DLk) and (DLk+1), the polarity of the capacitance within the parasitic capacitors (Cdp1 and Cdp2) is inverted during each horizontal period (H). As a result, the various pixel voltages charged within each liquid crystal cell can become offset.
During the data apply period (DAP) of a first frame (1F), pixel signals are applied to the kth and (k+1)th data lines (DLk and DLk+1) in accordance with the dot inversion method. Due to the aforementioned offset, changes in first and second effective voltages (EVa and EVb) of the first and the second liquid crystal cells A and B, respectively, are substantially the same.
During a blanking period (BP) succeeding the data apply period (DAP), however, the kth and (k+1)th data lines (DLk and DLk+1) are placed in a floating state wherein the first and second liquid crystal cells A and B are capacitively coupled with pixel signals applied during the nth horizontal period (Hn) of n number of horizontal periods. Accordingly, values of the first (negative) and second (positive) pixel voltages Vp1 and Vp2 associated with the nth horizontal period are maintained during the blanking period.
For example, during the nth horizontal period, an nth negative pixel signal is applied to the kth data line (DLk) while an nth positive pixel signal is applied to the (k+1)th data line (DLk+1). The brightness level represented by the nth positive polarity pixel signal (+Vp) is relatively higher than the brightness level represented by the nth negative polarity pixel signal (−Vp). Accordingly, the nh negative and positive pixel signals are applied to the kth and (k+1)th data lines (DLk and DLk+1), respectively, during the blanking period (BP). As a result, the first (negative) and second (positive) pixel voltages Vp1 and Vp2 are capacitively affected by the nth pixel signals. More specifically, the magnitude of the first negative pixel voltage Vp1 is positively decreased a first amount due to the first parasitic capacitor (Cpd1) while the magnitude of the first negative pixel voltage Vp1 is negatively increased a second amount, greater than the first amount, due to the second parasitic capacitor (Cpd2). Further, the magnitude of the positive pixel voltage Vp2 is negatively decreased a first amount due to the first parasitic capacitor (Cpd1) while the magnitude of the first negative pixel voltage Vp1 is positively increased a second amount, greater than the first amount, due to the second parasitic capacitor (Cpd2). Since an absolute value of the first negative pixel voltage (Vp1) decreases during the blanking period (BP) while an absolute value of the second positive pixel voltage (Vp2) increases during the blanking period (BP), the intensity to which the first liquid crystal cell (A) transmits light differs compared to the intensity to which the second liquid crystal cell (B) transmits light.
Based on the values of the pixel signals Vp applied to the first and second liquid crystal cells (A) and (B) via the kth data line DLk, and based on the first (negative) and second (positive) pixel voltages Vp1 and Vp2, respectively, charged within the first and second liquid crystal cells (A) and (B), respectively, during the blanking period (BP), the effective pixel voltages EVa and EVb of the first and second liquid crystal cells (A) and (B), respectively, are determined by the following equations:EVa=(1−t)×Vp+t×Vp1EVb=(1−t)×Vp+t×Vp2,wherein t represents the duration of the blanking period (BP) within of one frame period (1F) and (1−t) represents the duration of the data apply period (DAP) within one frame period (1F).
Accordingly, the intensity to which an ith horizontal having the first liquid crystal cell (A) line transmits light differs compared to the intensity to which an (i+1)th horizontal line having the second liquid crystal cell (B) transmits light during the blanking period (BP) and the horizontal stripe phenomenon is generated.
Referring to FIG. 6, the effect of the horizontal stripe phenomenon is similar to the effect of displaying a green (G) pattern along a vertical direction. Accordingly, the picture quality in the related art LCD device is deteriorated. Moreover, the effect of the horizontal stripe phenomenon becomes more apparent as the duration of the blanking period within the frame increases, as the difference between absolute values of the pixel signals supplied to adjacent ones of data lines increases, and as differences in the capacitance values of the first and second parasitic capacitors Cdp1 and Cdp2 increases.